Plural station memory data sharing system

ABSTRACT

A plural station memory data sharing system in which packets are sent/received between plural stations interconnected through communication lines. Each station has a unique station address value, and the time is made to correspond to each station address value. The internal clock ( 39 ) in each station indicates the same time and circulates from time T 00  to an upper limit time TM. When the internal clock ( 39 ) indicates a time corresponding to the station address value of a station, data stored in a memory at the address position corresponding to the station address value is buried in a packet and the packet is sent through a communication line. An allowance time error sensing circuit ( 34 ) compares the calculated correct time of the internal clock of the station and the time indicated by the internal clock, If the error is out of an allowance range, the internal clock ( 39 ) is forcedly calibrated to the correct time.

TECHNICAL FIELD

This invention relates to a system for sharing memory data of aplurality of stations in which all the stations can share the samememory data.

BACKGROUND ART

One of the joint applicants of the present application, STEP TECHINICACo. Ltd., filed a patent application relating to “an electronic wiredsystem based on automatic cyclical communication” which has been grantedas a patent under No. 2,994,589. This patent will be described withreference to FIG. 1. This electronic wired system is constituted by Nsets of terminal devices 2, a central unit 1 for controlling theterminal devices 2 and a common communication line 3 connecting thesetogether. Data at an input port 21 and an output port 22 of eachterminal device 2 is circulated through the terminal devices in the formof packets and stored in a memory 4 of the central unit 1 at arespective one of memory locations having addresses which correspond tothe terminal devices, respectively. In this electronic wired system,since transmission and reception of data is performed by means only ofhardware called “a state machine”, the speed of transmission andreception of data has been significantly increased as compared to thataccording to the conventional communication based on a programmedcontrol with a microprocessor. Furthermore, since data at the input port21 and the output port 22 of each terminal device is stored in thememory, the central unit 1 can read/write data at the output/input portof any terminal device substantially in real time.

In the case of this electronic wired system, however, there is a problemthat a given terminal device cannot read data from the input/output portof another terminal device or write data into such port, although thecentral unit 1 can read/write data at the output/input port of anyterminal device as described above. The feature that a given terminaldevice can read data from and/or write data into another terminal deviceis needed in the case where a system must operate as a whole with itsterminal devices acting one upon the other, such as in the case of aman-like robot or the like where a terminal device is provide for eachjoint.

Furthermore, there is another problem in the above-described electronicwired system that when the central unit 1 fails the entire system stopsfunctioning since no transmission and reception of packets is performed.

DISCLOSURE OF INVENTION

It is therefore an object of the present invention to provide a systemfor sharing memory data which obviates the above-mentioned problems ofthe conventional electronic wired system, enables its stations tocommunicate data to each other and keeps the entire system functioningeven when a station thereof stops functioning by causing the remainingstations to continue to function.

In order to achieve the above object, a memory data sharing systemaccording to the invention is a system for sharing memory data of aplurality of stations by transferring packets between the plurality ofstations connected to a communication line, which system ischaracterized:

-   -   in that each station is a memory-type station device which        comprises a memory, a user interface for enabling the memory to        be accessed from the exterior of the station, a transmission        state machine for transmitting a packet, a reception state        machine for receiving a packet, an internal clock, an allowable        time-error determination circuit, and an arbitration circuit for        arbitrating accesses from the transmission and reception state        machines and from the user interface;

in that specific station address values 00, 01, . . . , 0N are set tothe stations, respectively;

in that a sum of a time required to send a packet onto the communicationline and a time required for the packet to propagate on thecommunication line is selected to be a unit of time between timeinstants indicated by the internal clock;

in that each time instant (T₀₀, T₀₁, T₀₂, . . . , T_(0N)) is assigned toa respective one of the station address values;

in that the internal clocks of the stations in the system all indicatethe same time instant and each advances from the time instant T₀₀ to amaximum time instant T_(M) cyclically;

in that, when the internal clock indicates a time instant whichcorresponds to the station address value of a given station, data inthat memory address location of the memory which corresponds to thestation address value of the given station is read through thearbitration circuit and embedded in a packet which is then transmittedover the communication line;

in that, when a packet is received successfully, its transmission sourceis determined from the received packet, whereupon the data in thereceived packet is written through the arbitration circuit into thatmemory address location which corresponds to the station address valueof transmission source; and

in that the allowable time-error determination circuit compares acorrect time instant of the internal clock of the own station ascalculated from the unit of time with a time instant as indicated by theinternal clock and, if a difference between these time instants exceedsan allowable value, forces the time instant of the internal clock to becorrected to agree to the correct time instant.

According to this system, the specific station addresses 00, 01, . . . ,0N are set to the stations, respectively, and all the internal clocks inthe stations indicate the same time instant, i.e., one of T00, T01, . .. , T0N which correspond to the specific station address values 00, 01,. . . , 0N, respectively. The sum of the time required to send a packetonto the communication line and the time required for the packet topropagate on the communication line is selected to be a unit of time forthe internal clock. That is to say, the internal clock advances its timeinstant to the next time instant each time this one unit of time haslapsed. When the time instant indicated by the internal clock reachesthe maximum time instant T_(M), it then returns to a time instantcorresponding to 00, whereby the internal clock advances from the timeinstant T₀₀ to the time instant T_(M) cyclically. When the internalclock indicates a time instant which corresponds to the station addressvalue of a given station, data in that memory address location of thememory which corresponds to the station address value of that station isread through the arbitration circuit, which data is embedded in a packetand is then transmitted over the communication line. When a packet isreceived successfully, its transmission source is recognized from thereceived packet, and the data in the received packet is written throughthe arbitration circuit into that memory address location whichcorresponds to the station address value of the transmission source.When this process makes a round over the time instants T00 to TM, thememory data contained in those memory address locations in the memoriesof all the stations which correspond to each specific station addressvalue become identical. This is to say, from that moment, all thememories of the stations share the same memory content.

The allowable time-error determination circuit compares a correct timeinstant of the internal clock of the own station as calculated from theunit of time with a time instant as indicated by the internal clock and,if a difference between these time instants exceeds an allowable value,forces the time instant of the internal clock to be corrected to agreeto the correct time instant. Thus, it is ensured that all the stationskeep the same time instant within a range of the allowable value.

By employing the above structure, in the system for sharing memory dataof a plurality of stations, even if a station fails, the other stationscan continue to transmit and receive packets autonomously, so that thesystem can continue to function.

Another system for sharing memory data of a plurality of stationsaccording to the invention is characterized:

in that an I/O-type station device comprising an I/O terminal outputport, an I/O terminal input port, an output address setting circuit, anoutput-port data holding circuit, a transmission state machine fortransmitting a packet, a reception state machine for receiving a packet,an internal clock and an allowable time-error determination circuit isadditionally connected to the communication line;

in that, when the internal clock indicates a time instant whichcorresponds to the station address value of a given station composed ofthe I/O-type station device, data is read from the I/O terminal inputport of that station and embedded into a packet which is thentransmitted over the communication line; and

in that, when a packet is received successfully and when a preset valueto the output address setting circuit and the station address value of atransmission source of the received packet agree to each other, therelevant data in the received packet is held in the output-port dataholding circuit and supplied to the I/O terminal output port.

In this system, the I/O-type station device comprising the I/O terminaloutput port, the I/O terminal input port, the output address settingcircuit and the output-port data holding circuit has been connected inaddition to the memory-type station device which enables the user toread data from and write data to the memory in the station through theuser interface such as a microprocessor. In this system, the I/O-typestation device can perform reading/writing of memory data in thememory-type station device.

In either of the above-described systems for sharing memory data of aplurality of stations, in which a length of the data in the packet isfixed and in which the memory-type station device comprises a packettransmission number determination circuit for causing packets equal innumber to a number set to the packet transmission number determinationcircuit to be transmitted in succession from a time instantcorresponding to the station address value of the own station to therebyallow the memory-type station device to occupy a memory address rangewhich corresponds to a plurality of stations, when the internal clockindicates a time instant corresponding to the station address value ofthe own station, data is read from a memory address locationcorresponding to the station address value of the own station andembedded in a packet which is then transmitted. When the internal clockindicates the next time instant, data is read from a memory addresslocation corresponding to the next one of the station address value ofthe own station and embedded in a packet which is then transmitted. Inthis manner, packets equal in number to the number set to the packettransmission number determination circuit are transmitted, so that theamount of data which is written into other stations within one cycle ofthe internal clock can be increased by a factor equal to the number setto the packet transmission number determination circuit.

In either of the above-described systems for sharing memory data of aplurality of stations, in which a length of the data in the packet isvariable while information of the data length is added to the packet andin which the memory-type station device comprises a station addressoccupation size determination circuit which causes a packet having adata length set to the station address occupation size determinationcircuit to be transmitted from a time instant corresponding to thestation address value of the own station to thereby allow thememory-type station device to occupy a memory address range whichcorresponds to a plurality of stations, when the internal clockindicates a time instant corresponding to the station address value ofthe own station, data in the range from a start memory addresscorresponding to the station address value of the own station to amemory address corresponding to the station address value to which thevalue set to the station address occupation size determination circuithas been added is read at once and embedded in a packet which is thentransmitted. Thus, it becomes possible to write data, whose size isincreased by a factor equal to the value set to the station addressoccupation size determination circuit, in the other stations at oncewithin one cycle of the internal clock.

In any one of the above-described systems for sharing memory data of aplurality of stations, in which reception completion information fromother stations is added to the packet, and in which the memory-typestation device is further provided with a reception condition managingregister for managing a handshaking condition or a condition of thecommunication line in each cycle of the internal clock based on thereception completion information, even when the system is installed inan environment where packet transmission may be subjected to an externalinterference, it is possible to determine the quality in operation ofthe system in terms of whether such packet transmission has beeninterfered with. It may also be made possible to determine whether theshared data is that updated in the immediately preceding cycle of theinternal clock.

When the memory-type station device or the I/O-type station device forthe system for sharing memory data of a plurality of stations isconstituted by a semiconductor integrated circuit, it becomes compactand cost-efficient.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration showing the structure of a conventionalelectronic wired system;

FIG. 2 is an illustration showing the structure of a memory sharingsystem provided in accordance with a first embodiment of the invention;

FIG. 3 is an illustration showing the structure of a memory-type stationdevice used in each station of the system according to the firstembodiment;

FIG. 4 is an illustration showing a packet used in the system accordingto the first embodiment;

FIGS. 5 to 7 are illustrations explaining the operation of the memorysharing system according to the first embodiment;

FIG. 8 is an illustration showing the structure of a memory sharingsystem according to a second embodiment of the invention;

FIG. 9 is an illustration showing the structure of an I/O-type stationdevice used in a station of the system according the second embodiment;

FIG. 10 is an illustration showing the structure of a memory-typestation device used in the system according to a third embodiment of theinvention;

FIG. 11 is an illustration showing the structure of the memory sharingsystem according to the third embodiment;

FIG. 12 is an illustration explaining the operation of the memorysharing system according to the third embodiment;

FIG. 13 is an illustration showing the structure of a memory-typestation device used in the system according to a fourth embodiment ofthe invention;

FIG. 14 is an illustration showing the structure of the memory sharingsystem according to the fourth embodiment;

FIG. 15 is an illustration explaining the operation of the memorysharing system according to the fourth embodiment;

FIG. 16 is an illustration showing a packet used in the system accordingto the fourth embodiment;

FIG. 17 is an illustration showing another packet used in the systemaccording to the fourth embodiment;

FIG. 18 is an illustration showing the structure of a memory-typestation device used in the system according to a fifth embodiment of theinvention;

FIG. 19 is an illustration showing a packet used in the system accordingto the fifth embodiment; and

FIGS. 20 to 22 are illustrations explaining the operation of the memorysharing system according to the fifth embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

A system for sharing memory data of a plurality of stations will now bedescribed with reference to each of its five embodiments.

First Embodiment

A system for sharing memory data of a plurality of stations according toa first embodiment of the invention is a system in which each station iscomposed only of a memory-type station device 31 (see FIG. 2).

Each memory-type station device 31 is formed by a semiconductorintegrated circuit and comprises, as shown in FIG. 3, a user interface32, an allowable time-error determination circuit 34, a reception statemachine 35, a transmission state machine 36, an arbitration circuit 37,a memory 38 and an internal clock 39, all of which are constituted bydigital circuits each driven by a circuit-driving clock from a clocksource.

The internal clock 39 is constituted by an incrementing counter circuitin which its count value is increased from “0” and returned to “0” uponreaching the upper limit time “T_(M)” defined specifically to thissystem, whereby its time is advanced cyclically. When the time instantindicated by the internal clock 39 agrees to the time instantcorresponding to a station address value of this own station, a commandto start transmission is issued to the transmission state machine 36.

The transmission state machine 36 sends a memory address correspondingto the station address value and a read command RD to the arbitrationcircuit 37 to thereby obtain through the arbitration circuit 37 data tobe embedded into a packet from the memory 38, which packet is thentransmitted.

When a packet is received from another station, the reception statemachine 35 recognizes from the received packet its transmission sourceand then sends to the arbitration circuit 37 a memory addresscorresponding to the station address value of that transmission sourcetogether with the relevant data in the received packet and a writecommand WR to thereby complete writing of such information through thearbitration circuit 37 into the memory 38.

In addition, the reception state machine 35 signals the allowabletime-error determination circuit 34 of the time instant of thecompletion of reception by means of the station address value of thetransmission source of the received packet and a reception completionsignal.

The allowable time-error determination circuit 34 compares the correcttime instant of the internal clock of the own station as calculated withthe time instant as indicated by the internal clock 39 and, when thedifference exceeds an allowable value, forces the time instant of theinternal clock 39 to be corrected to agree to the correct time instant.

The memory-type station device 31 comprises a user interface 32 whichenables transmission and reception of data between a computer apparatusconnected to this memory-type station device 31 and the memory in theown station. This user interface 32 handles address bus data, data busdata, a read control signal RD and a write control signal WR.

The arbitration circuit 37 enables read and write accesses made by theuser to the memory 38 in the memory-type station device 31 through theuser interface 32 and accesses to the memory 38 by the transmissionstate machine 36 or the reception state machine 35 to be carried outwithout any conflict.

A packet used in this embodiment is shown in FIG. 4. This packet isformatted to be composed of a start pattern 41, a transmission-sourcestation address value 42, four-byte data 43 and a parity code 44.

The operation of the first embodiment will now be described for anexemplary system composed of four memory-type stations devices 31 withreference to FIGS. 5 to 7. As shown in FIG. 2, these memory-type stationdevices 31 are connected to the communication line 33 and given specificstation address values 00 to 03, respectively. FIGS. 5 to 7 show datacontents of the memories 38 of the respective station devices havingstation address values 00 to 03 for each time instant indicated by theinternal clocks.

The relationship between memory addresses of each memory 38 and thestation address values in the system is shown in FIG. 5. The memoryaddress location of the memory corresponding to the station addressvalue 00, which is indicated by “station address value 00 region”, isdefined by the memory addresses 0 to 3. The memory address location ofthe memory corresponding to the station address value 01, which isindicated by “station address value 01 region”, is defined by the memoryaddresses 4 to 7. Likewise, the memory address location corresponding tothe station address value 02 is defined by the memory addresses 8 to Band the memory address location corresponding to the station addressvalue 03 by the memory addresses C to F. In this manner, the memories ofall the memory-type stations devices 31 are given specific memoryaddresses, and each memory can hold the data of all the memories in thesystem.

Immediately after the start of the system, the internal clocks of therespective stations indicate different time instants and their memoriescontain different data, as shown in FIG. 5.

When the internal clock of the memory-type station device having stationaddress value 00 reaches a time instant T₀₀, this memory-type stationdevice having station address value 00 embeds the data contained inmemory addresses 0 to 3 into a packet and transmits the packet over thecommunication line 33.

Each of the three memory-type station devices 31 having station addressvalues 01 to 03 which have received the packet transmitted by thememory-type station device having station address value 00 writes thereceived data into memory addresses 0 to 3 of the memory of the ownstation.

In addition, each of the three memory-type station devices 31 havingstation address values 01 to 03 which have received the packettransmitted by the memory-type station device having station addressvalue 00 compulsorily corrects the internal clock 39 of its own stationif it is determined by the allowable time-error determination circuit 34that the time instant as indicated by the internal clock and the timeinstant as determined based on the time obtained by adding the timerequired for transmitting the packet of the received station addressvalue and the time required for its propagation together do not fallwithin an allowable error range.

Since each internal clock is thus corrected, the internal clocks 39 ofall the stations now indicate time instants T.sub.01 which agree to eachother within the allowable time-error range as shown in FIG. 6. Theinternal clocks of all the stations thus indicate the time instantT.sub.01, and the data contained in memory addresses 4 to 7 of thememory-type station device of the station address value 01 is embeddedin a packet which is then transmitted over the communication line 33.When the internal clocks reach time instant T.sub.02, the data containedin memory addresses 8 to B of the memory-type station device of thestation address value 02 is embedded in a packet which is thentransmitted. When the internal clocks reach time instant T.sub.03, thedata contained in memory addresses C to F of the memory-type stationdevice of the station address value 03 is embedded in a packet which isthen transmitted over the communication line 33.

The time instant indicated by each internal clock cyclically andconstantly changes from time instant T₀₀ to time instant T₀₃. The timeinstant T₀₃ in this first embodiment is, in general, defined for eachsystem as its specific upper-limit time instant T_(M). At the next timeinstant T₀₀ after one cycle of the internal clock, the data in therespective memories 30 in all the memory-type station devices are thesame.

Since an error in time of each internal clock is immediately correctedupon reception of each packet by the allowable time-error determinationcircuit 34 if the error exceeds the allowable error, such an error willnot be accumulated even when the cyclic operation of the internal clockcontinues, with the result that the internal clocks of all the stationscan indicate time instants which always agree to each other.

In the system according to this embodiment, even when the memory-typestation device of station address 01 fails or is disconnected by anaccident from the communication line, the internal clocks of thestations having station address values 00, 02 and 03 still continue toproceed and these stations do not stop transmitting packets. Thus, thesharing of memory data among the three remaining stations continues andno failure of the system as a whole may result.

As is clear from the block diagram of FIG. 3, the operation of thememory-type station device is effected not by the conventionalcommunication control with a microprocessor based on a control programbut by means only of hardware in the form of state machines, so that thetransmission rate of packets can be increased up to the upper-limittransmission capacity which the communication line has as a transmissionmedium.

When the transmission rate is selected to be 10 MBPS, since the packetin the present embodiment shown in FIG. 4 is composed of seven bytes (8bits×7=56 bits), the time required to transmit a packet is 5.6 microseconds (0.1_s×56 bits=5.6_(—)56 bits=5.6_s). When it is assumed thatthe required propagation time of the packet on the communication line 33is 1_s, one cycle time of the internal clock 39 is 6.6_s×4=26.4_s whichis sufficiently shorter as compared to the signal response time of 1_snormally required for the control of apparatuses such as a robot, sothat the response time in terms of the data shared by all the stationscan be treaded virtually as zero.

Each of the stations constituting this system can communicate data withany other station in the system within a time period which issubstantially zero and, in addition, all the memories hold the same datacontents, which means that the stations share a single memory.

Differently from the above-mentioned conventional electronic wiredsystem, in the system for sharing memory data of a plurality of stationsaccording to the present invention, there is no distinction betweenapparatuses such as the central unit and the station device and all thestations can communicate data to one another arbitrarily and freely.Therefore, even when any one of the stations fails during the operationof the system, the remaining stations do not stop their transmission ofpackets, so that the system can still continue to operate. Thus, therewill not arise the problem of the conventional electronic wired systemthat when the central unit stops operation the entire system also stopsoperation.

Second embodiment

A system for sharing memory data of a plurality of stations according toa second embodiment is a system which comprises two stations eachcomposed of the memory-type station device 31 and two stations eachcomposed of an I/O-type station device 91 (see FIG. 8).

Each I/O-type station device 91 is formed by a semiconductor integratedcircuit and comprises, as shown in FIG. 9, an I/O terminal output port92, an I/O terminal input port 93, an output address setting circuit 94,an output-port data holding circuit 95, a transmission state machine 36,a reception state machine 35, an internal clock 39 and an allowabletime-error determination circuit 34, all of which are constituted bydigital circuits each driven by a circuit-driving clock from a clocksource.

Unlike the memory-type station device 31, this I/O-type station device91 does not comprise the memory 38 and the arbitration circuit 37. Thereception state machine 35, the internal clock 39 and the allowabletime-error determination circuit 34 are the same in operation as thoseof the first embodiment.

In order to input “on/off states” of elements such as switches andsensors for the control of an apparatus to a computer system as controlsignal inputs in the form of digital information, the I/O-type stationdevice 91 is provided with the I/O terminal input port 93. There is alsoprovided the I/O terminal output port 92 for supplying from the computersystem control signal outputs for the control of the apparatus.

The I/O-type station device 91 of this embodiment comprises 32-bit I/Oterminal input port 93 corresponding to 4-byte data and 32-bit I/Oterminal output port 92 also corresponding to 4-byte data. In the systemaccording to this second embodiment, the memory-type station devices 31are given specific station address values 00 and 03, respectively, whilethe I/O-type station devices 91 are given specific station addressvalues 01 and 02, respectively.

In the system according to the present embodiment, the state of the I/Oterminal input port 93 of the I/O-type station device 91 having stationaddress value 01 is written into memory addresses 4 to 7 of the memory38 of each of the two memory-type station devices 31. Any one of thestations constituting this system can read the data written in thememory addresses 4 to 7 through the user interface 32 of the relevantmemory-type station device 31. In a similar manner, the state of the I/Oterminal input port 93 of the I/O-type station device 91 having stationaddress value 02 is written into memory addresses 8 to B of the memory38 of each of the two memory-type station devices 31, and any one of thestations constituting this system can read the data written in thememory addresses 8 to B through the user interface 32 of the relevantmemory-type station device 31.

The principle of operation of the system according to this secondembodiment will now be described.

When the internal clock 39 of the I/O-type station device 91 indicates atime instant which corresponds to the station address value of the ownstation, a transmission start signal is sent to the transmission statemachine 36, whereupon the transmission state machine 36 reads data fromthe I/O terminal input port 93, embeds the data in a packet andtransmits the packet.

The objective data to be supplied to the I/O terminal output port 92 isdetermined by a preset value from the exterior of the station.

When the reception state machine 35 receives a packet from anotherstation, the relevant data in the received packet is held by theoutput-port data holding circuit 95 in response to a coincidence signalsupplied to the circuit 95 if the preset value to the output addresssetting circuit 94 coincides to the station address value of thetransmission source. Then, the data held by the output-port data holdingcircuit 95 is supplied to the I/O terminal output port 92.

In the case where the preset value to the output address setting circuit94 of the I/O-type station device 91 having station address value 01 is“00”, when a packet transmitted through the communication line 33 fromthe memory-type station device 31 at time instant T₀₀ of the internalclock 39 is received, the I/O-type station device 91 having stationaddress value 01 can supply the content of the memory corresponding tothe station address value 00 to the I/O terminal output port 92.

More specifically, by selecting an output address value to be set to theoutput address setting circuit 94, that the data of the shared memory 38in the packet which corresponds to a station address value other thanthat of the own station can be obtained at the I/O terminal output port92. The same is true of the I/O-type station device 91 having stationaddress value 02.

In the case of the system according to this second embodiment, since thememory-type station device 31 and the I/O-type station device 91coexist, by assigning the I/O terminal input port 93 of the I/O-typestation device 91 to a control signal input for an apparatus to be usedas a control object and by assigning the I/O terminal output port 92 toits control signal output, these 32-bit control signal input and outputeach corresponding to four-byte data can be treated as the data of theshared memory of the entire system contained in the memory within thememory-type station device 31.

Third Embodiment

A system for sharing memory data of a plurality of stations according toa third embodiment is a system in which the number of packets which eachstation can transmit in succession can be set. According to this system,when the internal clock indicates the time instant which corresponds tothe station address value of the own station, packets equal in number toa number set to a packet transmission number determination circuit aretransmitted in succession.

A memory-type station device 31 used in this system is formed by asemiconductor integrated circuit, and its structure is as shown in FIG.10. As compared to the device of the first embodiment shown in FIG. 3,the transmission state machine 36 is added with a packet transmissionnumber determination circuit 101.

When the internal clock 39 indicates a time instant which corresponds tothe station address value of the own station, the transmission statemachine 36 transmits, in succession, packets equal in number to thenumber set to the packet transmission number determination circuit 101.The operation of the memory-type station devices 31 in other respects isthe same as that of the first embodiment.

The number of packets transmitted is determined by a preset value fromthe exterior of the station. When this preset value is “0” or “1”, thenumber of packets to be sent is defined as one. When the preset value tothe packet transmission number determination circuit 101 of thisembodiment is “0” or “1”, only one packet is transmitted, so that theoperations of such stations are all the same as that of the memory-typestation device of the first embodiment.

The format of packet used in this embodiment is the same as that of thefirst embodiment shown in FIG. 4. Also, the relation between the stationaddress values and the memory address locations is the same as that inthe first embodiment.

The operation of this embodiment will now be described for an exemplarysystem having three memory-type station devices 31 shown in 11 withreference to a timing chart of FIG. 12. The memory-type station devices31 are given specific station addresses 00, 01 and 03, respectively.

When the internal clock 39 reaches a time instant T₀₀, a packet istransmitted from the memory-type station device 31 of the stationaddress value 00. The data sent in this packet is the data in the memoryaddresses 0 to 3 of the memory 38 in the memory-type station device 31of the station address value 01.

When the internal clock 39 reaches a time instant T₀₀, a packet istransmitted from the memory-type station device 31 of the stationaddress value 01. The data contained in this packet is the data in thememory addresses 4 to 7 of the memory 38 in the memory-type stationdevice 31 of station address value 01.

As shown in FIG. 11, the preset value to the packet transmission numberdetermination circuit of the memory-type station device 31 of stationaddress value 01 is “2”. Therefore, the memory-type station device 31 ofthe station address value 01 also transmits a packet when the internalclock 39 reaches the next time instant T₀₂ as shown in FIG. 12. The datacontained in this packet is the data in memory addresses 8 to B of thememory 38 within the memory-type station device 31 of the stationaddress value 01.

When the internal clock 39 reaches, a time instant T₀₃, a packet istransmitted from the memory-type station device 31 of the stationaddress value 03. The data contained in this packet is the data in thememory addresses C to F of the memory 38 in the memory-type stationdevice 31 of station address value 03.

In the system according to this embodiment, as is appreciated from thesituation that a packet transmission is effected two times by thememory-type station device 31 of the station address value 01, a packettransmission is performed a plurality of times equal in number to thevalue set to the packet transmission number determination circuit, sothat the amount of data to be written into the memories of otherstations within one cycle of the internal clock can be increased by afactor equal to the value set to the packet transmission numberdetermination circuit.

Fourth Embodiment

A system for sharing memory data of a plurality of stations according toa fourth embodiment comprises a station address occupation sizedetermination circuit in each station. When the internal clock indicatesa time instant corresponding to the station address value of the ownstation, a packet in which data of a variable length to be transmittedis embedded and to which information about the data length set to thestation address occupation size determination circuit is added can betransmitted.

A memory-type station device 31 used in this system is formed by asemiconductor integrated circuit, and its structure is show in FIG. 13.When comparing with the structure of the first embodiment shown in FIG.3, the transmission state machine 36 is added with a station addressoccupation size determination circuit 131. For the calculation ofcorrect time of the internal clock of the own station, a valuerepresentative of the data length as received by the reception statemachine 35 is passed to the allowable time-error determination circuit34.

When the internal clock 39 indicates a time instant which corresponds tothe station address value of the own station, the transmission statemachine 36 embeds in a packet data having a length determined by thevalue set to the station address occupation size determination circuit131 and transmits the packet with information about the data lengthadded thereto. The allowable time-error determination circuit 34 refersto the value, which is fed from the reception state machine 35 andrepresentative of the data length of the received packet, for thecalculation of correct time of the internal clock of the own station.The operation of this device in other respects is the same as that ofthe first embodiment.

The station address occupation size is determined by a preset value fromthe exterior of the station. When the preset value is “0” or “1”, thedata length for a packet transmission by the relevant station is deemedas being “one-fold”. That is to day, the packet length is not increased,so that all the station devices operate in the same manner as thememory-type station device of the first embodiment. In the presentembodiment, when the data length is “one-fold”, the relationship betweenthe memory addresses of the memory 38 and the station address values inthis system is the same as that in the first embodiment.

The operation of this fourth embodiment will now be described for anexemplary system having three memory-type station devices 31 shown inFIG. 14 with reference to a timing chart of FIG. 15. The memory-typestation devices 31 are given specific station address values 00, 01 and03, respectively.

As shown in the timing chart of FIG. 15, when the internal clock 39reaches a time instant T₀₀, a packet in which four-byte data is embeddedand to which information indicating the “one-fold” data length is addedat a data-length designating portion 161 of the format shown in FIG. 16is transmitted from the memory-type station device 31 of the stationaddress value 00. The data contained in this packet is the four-bytedata from the memory addresses 0 to 3 of the memory 38 within thememory-type station device 31 of the station address value 00.

As shown in FIG. 14, the value set to the station address occupationsize determination circuit 131 of the memory-type station device 31 ofthe station address value 01 is “2”. When the internal clock 39 reachesa time instant T₀₁, the memory-type station device 31 of the stationaddress value 01 embeds, in a packet, eight-byte data from the memoryaddresses 4 to B of the memory 38 in the memory-type station device 31of the station address value 01 and transmits the packet in the formatshown in FIG. 17 to which “2” has been added at the data-lengthdesignating portion 161.

When the internal clock 39 reaches a time instant T₀₃, a packet in theformat shown in FIG. 16 is transmitted from the memory-type stationdevice 31 of the station address value 03. The data in this packet isfour-byte data from the memory addresses C to F of the memory 38 in thememory-type station device 31 of the station address value 03, and “1”is added to the packet as its data length.

In the system according to this embodiment, as will be appreciated fromthe transmission of the packet embedded with the data of two-fold lengthperformed by the memory-type station device 31 of the station addressvalue 01, an amount of data increased by a factor set to the stationaddress occupation size determination circuit is embedded in a singlepacket and transmitted, so that it becomes possible to write into thememories of the other stations at once within one cycle of the internalclock data of a size increased by the factor set to the station addressoccupation size determination circuit.

Fifth Embodiment

A system for sharing memory data of a plurality of stations according toa fifth embodiment comprises a reception condition managing register ineach memory-type station device. By means of this register, it becomespossible to monitor the state of sharing data in the system and thestate of connection of each station to the communication line.

The structure of this system is the same as that of the first embodimentshown in FIG. 2.

A memory-type station device 31 used in this system is formed by asemiconductor integrated circuit, and its structure is show in FIG. 18.This device comprises, in addition to the elements of the firstembodiment shown in FIG. 3, a reception condition managing register 181.This reception condition managing register 181 comprises two types offlag registers, i.e., type-A—A flag register and type-A–B flag registereach composed of four bits. A received reception answer code, atransmission source station address value and a reception completionsignal are passed from the reception state machine 35 to the receptioncondition managing register 181. A transmission answer code is passedfrom the reception condition managing register 181 to the transmissionstate machine 36. A transmission completion signal is passed from thetransmission state machine 36 to the reception condition managingregister 181. The user interface 32 is connected also to the receptioncondition managing register 181. Each packet which is handled by thetransmission state machine 36 and the reception state machine 35 isadded with an answer code 191 shown in FIG. 19. The operation of thisembodiment in other respects is the same as that of the firstembodiment.

The principle of operation of the system according to this fifthembodiment will now be described.

When the internal clock 39 indicates a time instant corresponding to thestation address value of the own station, the type-A flag statusinformation in the reception condition managing register 181 is added asthe answer code to a packet to be transmitted from the transmissionstate machine 36, and the packet is then transmitted.

When the transmission of the packet is completed, all the type-A andtype-B flag information in the reception condition managing register 181is reset to “0” by the transmission completion signal passed from thetransmission state machine 36 to the reception condition managingregister 181.

When the reception state machine 35 receives a packet, a bit of thetype-A flag information of the reception condition managing register 181at that position which corresponds to the station address value of thetransmission source is set to “1” by the reception answer code, thetransmission source station address value and the reception completionsignal which are passed from the reception state machine 35 to thereception condition managing register 181.

In this case, if that bit of the reception answer code which correspondsto the station address value of the own station is “1”, a bit of thetype-B flag information in the reception condition managing register 181at that position which corresponds to the station address value of thetransmission source is also set to “1”.

By the above-described setting operation to the reception conditionmanaging register 181, the type-A flag register indicates “those otherstations from which packets were successfully received”. The type-B flagregister indicates, based on the type-A flag status information held inthe other stations and sent from those station, “those other stationsfor which it has been acknowledged that the packet of the own stationsuccessfully reached and from which their packets were also successfullyreceived”, that is to say, “those other stations for each of whichhandshaking has been established” from the viewpoint of communicationtechnique.

The user interface 32 enables the user not only to access the memory 38through the arbitration circuit 37 but also to access the receptioncondition managing register 181 to read the type-A and the type-B flaginformation.

The change in state of the type-A and type-B flags in the receptioncondition managing registers 181 of the four memory-type station devices31 according to the present embodiment will now be described withreference to FIGS. 20, 21 and 22, in each of which the vertical axisrepresents the time indicated by the internal clock.

For the purpose of easy understanding, the following description of theoperation will be made concentrating only on the reception conditionmanaging register 181 in the memory-type station device 131 of thestation address value 01.

When the memory-type station device 31 of the station address value 01completes transmission of a packet, the type-A and the type-B flaginformation once indicates all “0” (see FIG. 20 at a).

When the memory-type station device 31 of the station address value 02completed transmission of a packet, the bit #2 of each of the type-Ainformation and the type-B information in the reception conditionmanaging register 181 of the station device of the station address value01 which has just received the packet is set (see FIG. 20 at b).

When the memory-type station device 31 of the station address value 03completed transmission of a packet, the bit #3 of each of the type-Ainformation and the type-B information in the reception conditionmanaging register 181 of the station device of the station address value01 which has just received the packet is set (see FIG. 20 at c).

When the memory-type station device 31 of the station address value 00completed transmission of a packet, the bit #0 of each of the type-Ainformation and the type-B information in the reception conditionmanaging register 181 of the station device of the station address value01 which has just received the packet is set (see FIG. 20 at d).

For the station of the station address value 01, the type-A flaginformation in the reception condition managing register 181 at the timewhen the internal clock reaches the time instant corresponding to thestation address value of the own station indicates “those other stationsfrom which packets were successfully received” in the previous onecycle, while the type-B flag register indicates “those stations for eachof which handshaking has been established” in the previous one cycle.

Next, the change in state of the reception condition managing register181 of the station of the station address value 01 will be describedwith reference to FIG. 21 for the case where the station of the stationaddress value 02 fails to effect a packet transmission due to sometrouble or interference. In this case, bits #2 of both the type-A andtype-B flag registers are not set as shown in FIG. 21 at b, c and d.Based on this, the user can recognize at the station of the stationaddress value 01 that the station of the station address value 02 doesnot respond.

The user can further recognize that the data at the memory addresslocation corresponding to the station address value 02 is not in theshared condition for the station of the station address value 01.

Next, the change in state of the flags will be described with referenceto FIG. 22 for the case where a packet transmitted from the station ofthe station address value 01 when its internal clock 39 indicates a timeinstant T₀₁, was not received by the other stations due to aninstantaneous accidental interference caused by impulse noise or thelike from the outside onto the communication line 33.

FIG. 22 shows at d that the type-A flag information indicates thatreception from the other stations has been performed successfully butthat the type-B flag information indicates that delivery of data to theother stations has failed. FIG. 22 also shows at e that the aboveabnormal condition was caused by an instantaneous accidentalinterference whereafter the normal condition resumed.

Although the operation of the reception condition monitoring register181 has been described in the above for the station having the stationaddress value 01, since the operation of the reception conditionmonitoring register 181 is identical in all the memory-type stationdevices, every station can determine the establishment of handshakingwith all of the other stations.

In the system according to the present embodiment, it is possible todetermine the quality in operation of the system in terms of whether theother stations are connected to the communication line and whether thetransmission of packet has been hampered. It is also possible todetermine whether the shared data is the newest one updated within thedirectly preceding cycle of the internal clock.

In the first to fifth embodiments, although the memory-type stationdevice and/or the I/O-type station device are each formed by asemiconductor integrated circuit, it will be apparent for those skilledin the art that such station device can be constituted by separateelements.

1. A system for sharing memory data of a plurality of stations in whichpackets are transferred between the plurality of stations connected to acommunication line (33) characterized: in that each station is amemory-type station device (31) which comprises a memory (38), a userinterface (32) for enabling said memory to be accessed from the exteriorof said station, a transmission state machine (36) for transmitting apacket, a reception state machine (35) for receiving a packet, a cyclicinternal clock (39) for tracking specific time instants assigned to eachstation and for tracking time instants when a packet is transmitted froma station to said communication line, an allowable time-errordetermination circuit (34) and an arbitration circuit (37) forarbitrating accesses from said transmission and reception state machines(36, 35) and from said user interface (32); in that specific stationaddress values 00, 01, . . . , 0N are set to said stations,respectively; in that a sum of a time required to transmit a packet ontosaid communication line (33) and a time required for said packet topropagate on said communication line (33) is selected to be a unit oftime between time instants indicated by said internal clock (39); inthat each time instant (T₀₀, T₀₁, T₀₂, . . . , T_(0N)) is assigned to arespective one of said station address values; in that said internalclocks (39) in said stations of said system all indicate the same time,instant and each advances from the time instant T₀₀ to a maximum timeinstant T_(M) cyclically; in that, when said internal clock (39)indicates a time instant which corresponds to the station address valueof a given station, data in that memory address location of said memorywhich corresponds to the station address value of said given station isread through said arbitration circuit (37) and embedded in a packetwhich is then transmitted over said communication line (33); in that,when a packet is received successfully, its transmission source isdetermined from the received packet, whereupon said data in the receivedpacket is written through said arbitration circuit (37) into that memoryaddress location which corresponds to the station address value of saidtransmission source; and in that said allowable time-error determinationcircuit (34) corrects the time instant of said internal clock based onthe difference between: a) a correct time instant of said internalclock; b) a time instant which is the sum of a time instant of thestation specified by the station address included in the packet actuallytransmitted by the other station, and time required for saidtransmission.
 2. A system for sharing memory data of a plurality ofstation according to claim 1, wherein a length of the data in the packetis fixed, said memory-type station device comprising a packettransmission number determination circuit (101) which causes packetsequal in number to a number set to said packet transmission numberdetermination circuit to be transmitted in succession from a timeinstant corresponding to the station address value of the own station tothereby allow the memory-type station device to occupy a memory addressrange which corresponds to a plurality of stations.
 3. A system forsharing memory data of a plurality of station according to claim 1,wherein a length of the data in the packet is variable while informationof the data length is added to said packet, said memory-type stationdevice comprising a station address occupation size determinationcircuit (131) which causes a packet having a data length set to saidstation address occupation size determination circuit to be transmittedfrom a time instant corresponding to the station address value of theown station to thereby allow the memory-type station device to occupy amemory address range which corresponds to a plurality of stations.
 4. Asystem for sharing memory data of a plurality of station according toclaim 1, wherein reception completion information from other stations isadded to the packet, and wherein said memory-type station device isfurther provided with a reception condition managing register (181)which manages a handshaking condition or a condition of saidcommunication line (33) in each cycle of said internal clock based onsaid reception completion information.
 5. A semiconductor integratedcircuit which constitutes said memory-type station device in a systemfor sharing memory data of a plurality of station according to claim 1.6. An electronic circuit for implementing said memory-type stationdevice in a system for sharing memory data of a plurality of stationaccording to claim
 1. 7. A system for sharing memory data of a pluralityof station according to claim 1, wherein an I/O-type station device (91)comprising an I/O terminal output port (92), an I/O terminal input port(93), an output address setting circuit (94), an output-port dataholding circuit (95), a transmission state machine (36) for transmittinga packet, a reception state machine (35) for receiving a packet, aninternal clock (39) and an allowable time-error determination circuit(34) is additionally connected to said communication line (33), wherein,when said internal clock (39) indicates a time instant which correspondsto the &tation address value of a given station composed of the I/O-typestation device (91), data is read from the I/O terminal input port (93)of said given station and embedded into a packet which is thentransmitted over said communication line (38), and wherein, when apacket is received successfully and when a preset value to said outputaddress setting circuit (94) and the station address value of atransmission source of the received packet agree to each other, therelevant data in the receive packet is held in said output-port dataholding circuit (95) and supplied to said I/O terminal output port (92).